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L6919E
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT
s s s s
s s s s s s
s s s s
2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD TRANSIENT RESPONSE INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT TTL-COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT FROM 0.800V TO 1.550V WITH 25mV STEPS DYNAMIC VID MANAGEMENT 0.6% OUTPUT VOLTAGE ACCURACY 10% ACTIVE CURRENT SHARING ACCURACY DIGITAL 2048 STEP SOFT-START OVERVOLTAGE PROTECTION OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S R dsON OR A SENSE RESISTOR OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 200kHz POWER GOOD OUTPUT AND INHIBIT FUNCTION REMOTE SENSE BUFFER PACKAGE: SO-28
SO-28 ORDERING NUMBERS:L6919E L6919ETR
APPLICATIONS s POWER SUPPLY FOR SERVERS AND WORKSTATIONS s POWER SUPPLY FOR HIGH CURRENT MICROPROCESSORS s DISTRIBUTED POWER SUPPLY BLOCK DIAGRAM
O S C / I NH S GN D
DESCRIPTION The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. The device implements a dual-phase step-down controller with a 180 phase-shift between each phase. A precise 5-bit digital to analog converter (DAC) allows adjusting the output voltage from 0.800V to 1.550V with 25mV binary steps managing On-The-Fly VID code changes. The high precision internal reference assures the selected output voltage to be within 0.6%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load over current and load over/under voltage. An internal crowbar is provided turning on the low side mosfet if an over-voltage is detected. In case of over-current, the system works in Constant Current mode.
VC C D R BOO T 1
2 P H AS E O S C IL L ATOR
L O G IC PW M
PW M1
A DA PTIV E A NT I CRO SS CO ND UCT IO N
PGO O D
HS
U T E1 GA
PHAS E1
C U RR EN T COR R EC TI ON
DIGIT AL SOFT- START
LOGIC AN D P ROTE CTION S
CH1 O CP
LS
L GAT E1 ISE N1
V CC V CC DR TO TAL C UR REN T C U R R EN T AV G
CUR REN T REA DIN G
PGN DS1 PGN D
VID 4 VID 3 VID 2 VID 1 VID 0
D AC
CH 2 OC P C H1 OCP
CUR REN T REA DIN G
PGN DS2 ISE N2
CU R R EN T C OR R EC TI ON
32k 3 2k I FB
CH2 O CP
FB G FB R
LO G IC PW M A DA PT IV E A N T I CRO SS CO N DU CT IO N
LS
L GAT E2
PHAS E2
3 2k
PW M2
HS
32k
R EMO TE BU FFE R
ERR OR A MPL IF IER
U GA T E2
Vc c
BOO T 2
V S EN
FB
COM P
V cc
September 2003
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L6919E
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc, VCCDR VBOOT-VPHASE VUGATE1-VPHASE1 VUGATE2-VPHASE2 LGATE1, PHASE1, LGATE2, PHASE2 to PGND VID0 to VID4 All other pins to PGND Vphase UGATEx Pin OTHER PINS Sustainable Peak Voltage t < 20ns @ 600kHz Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002"Human Body Model" Acceptance Criteria: "Normal Performance" to PGND Boot Voltage Parameter Value 15 15 15 -0.3 to Vcc+0.3 -0.3 to 5 -0.3 to 7 26 1000 2000 Unit V V V V V V V V V
THERMAL DATA
Symbol Rth j-amb Tmax Tstorage Tj PMAX Parameter Thermal Resistance Junction to Ambient Maximum junction temperature Storage temperature range Junction Temperature Range Max power dissipation at Tamb = 25C Value 60 150 -40 to 150 0 to 125 2 Unit C/W C C C W
PIN CONNECTION
LGATE1 VCCDR PHASE1 UGATE1 BOOT1 VCC SGND COMP FB VSEN FBR FBG ISEN1 PGNDS1
1 2 3 4 5
28 27 26 25 24
PGND LGATE2 PHASE2 UGATE2 BOOT2 PGOOD VID4 VID3 VID2 VID1 VID0 OSC / INH / FAULT ISEN2 PGNDS
7 8 9 10 11 12 13 14
L6919E
6
23 22 21 20 19 18 17 16 15
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L6919E
ELECTRICAL CHARACTERISTICS VCC = 12V 15%, TJ = 0 to 70C unless otherwise specified
Symbol Parameter Test Condition Min Typ Max Unit
Vcc SUPPLY CURRENT ICC ICCDR IBOOTx Vcc supply current VCCDR supply current Boot supply current HGATEx and LGATEx open VCCDR=VBOOT=12V LGATEx open; VCCDR=12V HGATEx open; PHASEx to PGND VCC=VBOOT=12V 7.5 2 0.5 10 3 1 12.5 4 1.5 mA mA mA
POWER-ON Turn-On VCC threshold Turn-Off VCC threshold Turn-On VCCDR Threshold Turn-Off VCCDR Threshold OSCILLATOR/INHIBIT/FAULT fOSC INH dMAX Initial Accuracy Inhibit threshold Maximum duty cycle OSC = OPEN OSC = OPEN; Tj=0C to 125C ISINK=5mA OSC = OPEN; IFB = 0 OSC = OPEN; IFB = 70A Vosc FAULT Ramp Amplitude Voltage at pin OSC OVP or UVP Active 4.75 135 127 0.5 72 30 80 40 3 5.0 5.25 150 165 178 kHz kHz V % % V V VCC Rising; VCCDR=5V VCC Falling; VCCDR=5V VCCDR Rising VCC=12V VCCDR Falling VCC=12V 8.2 6.5 4.2 4.0 9.2 7.5 4.4 4.2 10.2 8.5 4.6 4.4 V V V V
REFERENCE AND DAC Output Voltage Accuracy IDAC VID pull-up Current VID pull-up Voltage ERROR AMPLIFIER DC Gain SR Slew-Rate COMP=10pF 80 15 dB V/s VID0, VID1, VID2, VID3, VID4 see Table1; FBR = VOUT; FBG = GND VIDx = GND VIDx = OPEN -0.6 0.6 %
4 2.9
5 -
6 3.3
A V
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER) DC Gain CMRR SR Common Mode Rejection Ratio Slew Rate VSEN=10pF 1 40 15 V/V dB V/s
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L6919E
ELECTRICAL CHARACTERISTICS (continued) VCC = 12V 15%, TJ = 0 to 70C unless otherwise specified
Symbol Parameter Test Condition Min Typ Max Unit
DIFFERENTIAL CURRENT SENSING IISEN1, IISEN2 IPGNDSx IISEN1, IISEN2 IFB Bias Current Bias Current Bias Current at Over Current Threshold Active Droop Current ILOAD 0% ILOAD = 100% ILOAD = 0 45 45 80 50 50 85 0 50 55 55 90 1 52.5 A A A A A
47.5
GATE DRIVERS tRISE HGATE IHGATEx RHGATEx tRISE LGATE ILGATEx RLGATEx High Side Rise Time High Side Source Current High Side Sink Resistance Low Side Rise Time Low Side Source Current Low Side Sink Resistance VBOOTx-VPHASEx=10V; CHGATEx to PHASEx=3.3nF VBOOTx-VPHASEx=10V VBOOTx-VPHASEx=12V; VCCDR=10V; CLGATEx to PGNDx=5.6nF VCCDR=10V VCCDR=12V 0.7 1.5 15 2 2 30 1.8 1.1 1.5 2.5 55 30 ns A ns A
PROTECTIONS PGOOD PGOOD OVP UVP Upper Threshold (VSEN/DAC Output) Lower Threshold (VSEN/DAC Output) Over Voltage Threshold (VSEN) Under Voltage Trip (VSEN/DAC Output) VSEN Rising VSEN Falling VSEN Rising VSEN Falling IPGOOD = -4mA VPGOOD = 5V 108 84 1.915 55 60 112 88 116 92 2.05 65 0.4 1 % % V % V A
VPGOODL PGOOD Voltage Low IPGOODH PGOOD Leakage
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L6919E
Table 1. Voltage Identification (VID) Codes
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Voltage (V) 1.575 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Voltage (V) 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 Shutdown
The device automatically regulates 25mV higher than the Hammer specs avoiding the use of any external offset resistor
Reference Schematic
Vin GNDin
CIN
VCCDR VCC
2
6
BOOT1
5 4
24 25
BOOT2
UGATE1
UGATE2
HS1 L1
PHASE1
HS2
PHASE2
3
LGATE1
26
LGATE2
L2 COUT LOAD
LS1
ISEN1
1 13 Rg
PGNDS1
27
ISEN2
LS2
16 Rg
14 Rg S4 S3 S2 S1 S0
VID4
L6919E 15
28 23 10
PGNDS2
PGND
Rg
22
VID3
PGOOD
21
VID2
PGOOD
VSEN
20
VID1
19
VID0 FB
RFB
18
OSC / INH
9 RF CF
COMP
17
SGND
7 11
FBR
12
8
FBG
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L6919E
PIN FUNCTION
N 1 2 3 4 5 Name LGATE1 VCCDR PHASE1 UGATE1 BOOT1 Description Channel 1 LS driver output. A little series resistor helps in reducing device-dissipated power. LS drivers supply: it can be varied from 5V to 12V buses. Filter locally with at least 1F ceramic cap vs. PGND. Channel 1 HS driver return path. It must be connected to the HS1 mosfet source and provides the return path for the HS driver of channel 1. Channel 1 HS driver output. A little series resistor helps in reducing device-dissipated power. Channel 1 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode to VCC (cathode vs. boot). Device supply voltage. The operative supply voltage is 12V 10%. Filter with 1F (Typ.) capacitor vs. GND. All the internal references are referred to this pin. Connect it to the PCB signal ground. This pin is connected to the error amplifier output and is used to compensate the control feedback loop. This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. A current proportional to the sum of the current sensed in both channel is sourced from this pin (50A at full load, 70A at the Constant Current threshold). Connecting a resistor between this pin and VSEN pin allows programming the droop effect. Manages Over&Under-voltage conditions and the PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for Remote Sense of the regulated voltage. If no Remote Sense is implemented, connect it directly to the regulated voltage in order to manage OVP, UVP and PGOOD. Connecting 1nF capacitor max vs. SGND can help in reducing noise injection. Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to perform a remote sense. If no remote sense is implemented, connect directly to the output voltage (in this case connect also the VSEN pin directly to the output regulated voltage). Remote sense buffer inverting input. It has to be connected to the negative side of the load to perform a remote sense. Pull-down to ground if no remote sense is implemented. Channel 1 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg. The net connecting the pin to the sense point must be routed as close as possible to the PGNDS net in order to couple in common mode any picked-up noise. Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up noise. Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up noise. Channel 2 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg. The net connecting the pin to the sense point must be routed as close as possible to the PGNDS net in order to couple in common mode any picked-up noise.
6 7 8 9
VCC GND COMP FB
10
VSEN
11
FBR
12
FBG
13
ISEN1
14
PGNDS1
15
PGNDS2
16
ISEN2
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L6919E
PIN FUNCTION (continued)
N 17 Name OSC/INH FAULT Description Oscillator pin. It allows programming the switching frequency of each channel: the equivalent switching frequency at the load side results in being doubled. Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin with an internal gain of 6kHz/A (See relevant section for details). If the pin is not connected, the switching frequency is 150kHz for each channel (300kHz on the load). The pin is forced high (5V Typ.) when an Over/Under Voltage is detected; to recover from this condition, cycle VCC. Forcing the pin to a voltage lower than 0.6V, the device stop operation and enter the inhibit state. Voltage IDentification pins. Internally pulled-up, connect to GND to program a `0' while leave floating to program a `1'. They are used to program the output voltage as specified in Table 1 and to set the PGOOD, OVP and UVP thresholds. The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of any external set-up resistor. This pin is an open collector output and is pulled low if the output voltage is not within the above specified thresholds and during soft start. It cannot be pulled-up above 5V. If not used may be left floating. Channel 2 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF typ.) to the PHASE2 pin and through a diode to VCC (cathode vs. boot). Channel 2 HS driver output. A little series resistor helps in reducing device-dissipated power. Channel 2 HS driver return path. It must be connected to the HS2 mosfet source and provides the return path for the HS driver of channel 2. Channel 2 LS driver output. A little series resistor helps in reducing device-dissipated power. LS drivers return path. This pin is common to both sections and it must be connected through the closest path to the LS mosfets source pins in order to reduce the noise injection into the device.
18-22
VID4-0
23
PGOOD
24
BOOT2
25 26 27 28
UGATE2 PHASE2 LGATE2 PGND
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L6919E
DEVICE DESCRIPTION The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses. The output voltage of the converter can be precisely regulated, programming the VID pins, from 0.825V to 1.575V with 25mV binary steps, with a maximum tolerance of 0.6% over temperature and line voltage variations. The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of any external set-up resistor. The device manages On-The-Fly VID Code changes stepping to the new configuration following the VID table with no need for external components. The device provides an average current-mode control with fast transient response. It includes a 150kHz free-running oscillator. The error amplifier features a 15V/s slew rate that permits high converter bandwidth for fast transient performances. Current information is read across the lower mosfets RdsON or across a sense resistor in fully differential mode. The current information corrects the PWM output in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at 10% over static and dynamic conditions. The device protects against Over-Current, with an OC threshold for each phase, entering in constant current mode. Since the current is read across the low side mosfets, the constant current keeps constant the bottom of the inductors current triangular waveform. When an under voltage is detected the device latches and the FAULT pin is driven high. The device performs also Over-Voltage protection that disables immediately the device turning ON the lower driver and driving high the FAULT pin. OSCILLATOR The switching frequency is internally fixed at 150kHz. Each phase works at the frequency fixed by the oscillator so that the resulting switching frequency at the load side results in being doubled. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 25 A (Fsw=150kHz) and may be varied using an external resistor (ROSC) connected between OSC pin and GND or Vcc. Since the OSC pin is maintained at fixed voltage (Typ. 1.237V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 6KHz/A. In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships: kH z 1.237 7.422 10 R O SC vs. GND: f S = 150 kHz + --------------- 6 ---------- = 150kHz + ----------------------------A R ( K ) R
O SC O SC 7 6
12 - 1.237 kHz 6.457 10 R O SC vs. 12V: f S = 150kHz - -------------------------- 6 ---------- = 150 kHz - ----------------------------A R O SC R O SC ( K ) Note that forcing a 25A into this pin, the device stops switching because no current is delivered to the oscillator. Figure 1. ROSC vs. Switching Frequency
14000 800
Rosc(K ) vs. GND
12000
700 600 500 400 300 200 100 0 150
Rosc(K ) vs. 12V
10000 8000 6000 4000 2000 0 25 50 75 100 125 150
250
350
450
550
650
Frequency (KHz)
Frequency (KHz)
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L6919E
DIGITAL TO ANALOG CONVERTER The built-in digital to analog converter allows the adjustment of the output voltage from 0.800V to 1.550V with 25mV as shown in the previous table 1. The internal reference is trimmed to ensure output voltage precision of 0.6% and a zero temperature coefficient around 70C. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5A current generator up to 3.0V Typ); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. Programming the "11111" code, the device enters the NOCPU mode: all mosfets are turned OFF and protections are disabled. The condition is latched. The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the Over / Under Voltage protection (OVP/UVP) thresholds. DYNAMIC VID TRANSITION The device is able to manage On-The-Fly VID Code changes that allow Output Voltage modification during normal device operation. The device checks every clock cycle (synchronously with the PWM ramp) for VID code modifications. Once the new code is stable for more than one clock cycle, the reference steps up or down in 25mV increments every clock cycle until the new VID code is reached. During the transition, VID code changes are ignored; the device re-starts monitoring VID after the transition has finished. PGOOD, signal is masked during the transition and it is re-activated after the transition has finished while OVP / UVP are still active. Figure 2. Dynamic VID transition
VID
Reference
25mV steps transition
t
VOUT
t
t
1 Clock Cycle Blanking Time
DRIVER SECTION The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the RdsON), maintaining fast switching transition. The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VCCDRV pin is required to start operations of the device. The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanoseconds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet gate drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the inductor is negative, the source of high-side mosfet will never drop.
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L6919E
Figure 3. Drivers peak current: High Side (left) and Low Side (right)
CH3 = HGATE1; CH4 = HGATE2
CH3 = LGATE1; CH4 = LGATE2
To allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. Several combination of supply can be chosen to optimize performance and efficiency of the application. Power conversion is also flexible; 5V or 12V bus can be chosen freely. The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capacitive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with VBOOT -VPHASE = 12V; similarly, for the lower drivers, the source current is 2.4A while the sink current is 2A with VCCDR = 12V. CURRENT READING AND OVER CURRENT The current flowing trough each phase is read using the voltage drop across the low side mosfets RdsON or across a sense resistor (RSENSE) and internally converted into a current. The Tran conductance ratio is issued by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points. The full differential current reading rejects noise and allows to place sensing element in different locations without affecting the measurement's accuracy. The current reading circuitry reads the current during the time in which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two pins at the same voltage sinking from the ISENx pin the necessary current (Needed if low-side mosfet RdsON sense is implemented to avoid absolute maximum rating overcome on ISENx pin). The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and negative current. This circuit reproduces the current flowing through the sensing element using a high speed Track & Hold Tran conductance amplifier. In particular, it reads the current during the second half of the OFF time reducing noise injection into the device due to the mosfet turn-on (See fig. 4). Track time must be at least 200ns to make proper reading of the delivered current This circuit sources a constant 50A current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following equation: R SENSE I PHASE I ISENx = 50A + ---------------------------------------------- = 50 A + I INFO x Rg
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L6919E
Figure 4. Current Reading Timing (Left) and Circuit (Right)
ILS1
LGATEX
ILS2
Rg ISENX IISENx
Total current information
Rg PGNDSX
Track & Hold
50A
Where RSENSE is an external sense resistor or the rds,on of the low side mosfet and Rg is the transconductance resistor used between ISENx and PGNDSx pins toward the reading points; IPHASE is the current carried by each phase and, in particular, the current measured in the middle of the oscillator period The current information reproduced internally is represented by the second term of the previous equation as follow: R SENSE I PHASE I INFO x = ---------------------------------------------Rg Since the current is read in differential mode, also negative current information is kept; this allow the device to check for dangerous returning current between the two phases assuring the complete equalization between the phase's currents. From the current information of each phase, information about the total current delivered (IFB =IINFO1 +IINFO2) and the average current for each phase (IAVG =(IINFO1 +IINFO2)/2 ) is taken. IINFOX is then compared to IAVG to give the correction to the PWM output in order to equalize the current carried by the two phases. The transconductance resistor Rg can be designed in order to have current information of 25A per phase at full nominal load; the over current intervention threshold is set at 140% of the nominal (IINFOx = 35A). According to the above relationship, the over current threshold (IOCPx) for each phase, which has to be placed at one half of the total delivered maximum current, results: 35 A Rg I OCPx = -------------------------R S ENSE I OCP x R SE NSE Rg = -----------------------------------------35 A
Since the device senses the output current across the low-side mosfets (or across a sense resistors in series with them) the device limits the bottom of the inductor current triangular waveform: an over current is detected when the current flowing into the sense element is greater than IOCPx (IINFOx > 35A). Introducing now the maximum ON time dependence with the delivered current (where T is the switching period T=1/fSW): 0.80 T I F B = 0 A R SENSE T ON,MAX = 0.80 - ( I FB 5.73 k ) T = 0.80 - --------------------- I OUT 5.73k T Rg 0.40 T I F B = 7 0A This linear dependence has a value at zero load of 0.80*T and at maximum current of 0.40*T typical and results in two different behaviors of the device:

RSENSE
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IPHASE
L6919E
1. TON Limited Output Voltage. This happens when the maximum ON time is reached before the current in each phase reaches IOCPx (IINFOx < 35A). Figure 5a shows the maximum output voltage that the device is able to regulate considering the TON limitation imposed by the previous relationship. If the desired output characteristic crosses the TON limited maximum output voltage, the output resulting voltage will start to drop after crossing. In this case, the device doesn't perform constant current limitation but only limits the maximum ON time following the previous relationship. The output voltage follows the resulting characteristic (dotted in Figure 5b) until UVP is detected or anyway until IFB = 70A. Figure 5. TON Limited Operation
VOUT 0.80*VIN VOUT 0.80*VIN
TON Limited Output characteristic
Resulting Output characteristic Desired Output characteristic and UVP threshold
0.40*VIN
0.40*VIN
IOCP=2*IOCPx (IFB=70A)
IOUT
IOCP=2*IOCPx (IFB=70A)
IOUT
a) Maximum output Voltage
b) TON Limited Output Voltage
2. Constant Current Operation This happens when ON time limitation is reached after the current in each phase reaches I OCPx (IINFOx>35A). The device enters in Quasi-Constant-Current operation: the low-side mosfets stays ON until the current read becomes lower than IOCPx (IINFOx < 35A) skipping clock cycles. The high side mosfets can be turned ON with a TON imposed by the control loop at the next available clock cycle and the device works in the usual way until another OCP event is detected. This means that the average current delivered can slightly increase also in Over Current condition since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the IOCPx bottom. The worst-case condition is when the ON time reaches its maximum value. When this happens, the device works in Constant Current and the output voltage decrease as the load increase. Crossing the UVP threshold causes the device to latch (FAULT pin is driven high). Figure 6 shows this working condition It can be observed that the peak current (Ipeak) is greater than the IOCPx but it can be determined as follow: V IN - Vo ut M IN V IN - Vo ut M IN Ipea k = I OCPx + -------------------------------------- Ton M AX = I OCPx + -------------------------------------- 0.40 T L L Where VoutMIN is the minimum output voltage (VID-30% as follow). The device works in Constant-Current, and the output voltage decreases as the load increase, until the output voltage reaches the Under-Voltage threshold (VoutMIN). When this threshold is crossed, all mosfets are turned off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation. The maximum average current during the Constant-Current behavior results:

Ipe ak - I OCP x I M AX,TOT = 2 IMA X + 2 IOCPx + ------------------------------------2

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L6919E
Figure 6. Constant Current operation
Ipeak IMAX IOCPx
UVP
Vout
Droop effect
TonMAX
TonMAX
(IFB=50A)
Iout IMAX,TOT IOCP=2*IOCPx (IFB=70A)
a) Maximum current for each phase
b) Output Characteristic
In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed (TonMAX) while the OFF time depends on the application: Ipe ak - I OCP x T O FF = L ------------------------------------V OUT 1 f = ----------------------------------------T ONm a x + T O FF
Over current is set anyway when I INFOx reaches 35A (IFB = 70A). The full load value is only a convention to work with convenient values for I FB. Since the OCP intervention threshold is fixed, to modify the percentage with respect to the load value, it can be simply considered that, for example, to have on OCP threshold of 170%, this will correspond to IINFOx = 35A (IFB = 70A). The full load current will then correspond to IINFOx = 20.6A (IFB = 41.1A). Integrated Droop Function The device uses a droop function to satisfy the requirements of high performance microprocessors, reducing the size and the cost of the output capacitor. This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current As shown in figure 7, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. In practice the droop function introduces a static error (VDROOP in figure 8) proportional to the output current. Since the device has an average current mode regulation, the information about the total current delivered is used to implement the Droop Function. This current (equal to the sum of both IINFOx) is sourced from the FB pin. Connecting a resistor between this pin and VOUT, the total current information flows only in this resistor because the compensation network between FB and COMP has always a capacitor in series (See fig. 8). The voltage regulated is then equal to: VOUT = VID - RFB * IFB Since IFB depends on the current information about the two phases, the output characteristic vs. load current is given by: R SENSE V OUT = VID - R FB --------------------- I OUT Rg
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Figure 7. Output transient response without (a) and with (b) the droop function
ESR DROP ESR DROP
VMAX VDROOP
VNOM
VMIN
(a)
(b)
Figure 8. Active Droop Function Circuit
VDROOP To VOUT RFB COMP FB
Total Current Info (IINFO1+IINFO2)
Ref
The feedback current is equal to 50A at nominal full load (IFB = IINFO1 + IINFO2) and 70A at the OC intervention threshold, so the maximum output voltage deviation is equal to: VFULL_POSITIVE_LOAD = -RFB * 50A VOC_INTERVENTION = -RFB * 70A
Droop function is provided only for positive load; if negative load is applied, and then IINFOx < 0, no current is sunk from the FB pin. The device regulates at the voltage programmed by the VID. REMOTE VOLTAGE SENSE A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without any additional external components. In this way, the output voltage programmed is regulated between the remote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. If remote sense is not required, it is enough connecting RFB directly to the regulated voltage: VSEN becomes not connected and still senses the output voltage through the remote buffer. In this case the FBG and FBR pins must be connected anyway to the regulated voltage (See figure 10). The remote buffer is included in the trimming chain in order to achieve 0.5% accuracy on the output voltage when the RB Is used: eliminating it from the control loop causes the regulation error to be increased by the RB offset worsening the device performances.
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Figure 9. - Remote Buffer Connections
Reference ERROR AMPLIFIER
Reference
REMOTE BUFFER
REMOTE BUFFER
64k 64k
FBR
IFB
64k 64k 64k 64k
FBG VSEN
IFB
ERROR AMPLIFIER
64k 64k
FBG VSEN FB COMP
FBR
FB
COMP
RFB
Remote VOUT Remote Ground
CF
RF
RFB
CF
RF
VOUT
RB used (0.5% Accuracy)
RB Not Used
OUTPUT VOLTAGE MONITOR AND PROTECTIONS The device monitors through pin VSEN the regulated voltage in order to build the PGOOD signal and manage the OVP / UVP conditions. Power good output is forced low if the voltage sensed by VSEN is not within 12% (Typ.) of the programmed value. It is an open drain output and it is enabled only after the soft start is finished (2048 clock cycles after startup). During Soft-Start this pin is forced low. Under voltage protection is provided. If the output voltage monitored by VSEN drops below the 60% of the reference voltage for more than one clock period, the device turns off all mosfets and the OSC/FAULT is driven high (5V). The condition is latched, to recover it is required to cycle the power supply. Over Voltage protection is also provided: when the voltage monitored by VSEN reaches the OVP threshold VOVP the controller permanently switches on both the low-side mosfets and switches off both the high-side mosfets in order to protect the load. The OSC/ FAULT pin is driven high (5V) and power supply (Vcc) turn off and on is required to restart operations. The over voltage percentage is then set by the ratio between the fixed OVP threshold VOVP and the reference programmed by VID: V O VP O VP [ % ] = ---------------------------------------------------------------------- 100 Re feren ceVo ltage ( VID ) Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than the output voltage reaches 0.6V). The reference used in this case to determine the UV thresholds is the increasing voltage driven by the 2048 soft start digital counter while the reference used for the OV threshold is the final reference programmed by the VID pins. SOFT START AND INHIBIT At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in 2048 clock periods as shown in figure 10. Once the soft start begins, the reference is increased: upper and lower MOS begin to switch and the output voltage starts to increase with closed loop regulation. At the end of the digital soft start, the Power Good comparator is enabled and the PGOOD signal is then driven high (See fig. 10). The Under Voltage comparator is enabled when the reference voltage reaches 0.6V. The Soft-Start will not take place, if both VCC and VCCDR pins are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of the two supplies the device shuts down. Forcing the OSC/INH pin to a voltage lower than 0.6V (Typ.) disables the device: all the power mosfets and protections are turned off until the condition is removed.
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Figure 10. Soft Start
VCC=VCCDR
Turn ON threshold
VLGATEx
t
VOUT
t
PGOOD
t
2048 Clock Cycles
t
Timing Diagram
Acquisition: (CH1=LGATEx; CH2=VCC; CH3=VOUT;
INPUT CAPACITOR The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as reported in figure 11. Considering the dual-phase topology, the input RMS current is highly reduced comparing with a single phase operation. Figure 11. Input RMS Current vs. Duty Cycle (D) and Driving Relationships
Rms Current Normalized (IRMS/IOUT)
0.50
Single Phase
Dual Phase 0.25
I rms =
I OUT 2D (1 - 2D) if D < 0.5 2 I OUT (2D - 1) (2 - 2D) if D > 0.5 2
0.25 0.50 0.75 Duty Cycle (VOUT/VIN)
It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst case condition that happens for D = 0.25 and D = 0.75. The power dissipated by the input capacitance is then equal to: P RM S = ESR ( I RM S )
2
Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the high RMS value needed by the CPU power supply application and also to minimize components cost, the input capacitance is realized by more than one physical capacitor. The equivalent RMS current is simply the sum of the single capacitor's RMS current. Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible
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to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high frequency noise decoupling, noise generated by parasitic components along power path. OUTPUT CAPACITOR Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the range of tenth A/s, the output capacitor is a basic component for the fast response of the power supply. Dual phase topology reduces the amount of output capacitance needed because of faster load transient response (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180 phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage ripple. When a load transient is applied to the converter's output, for first few microseconds the current to the load is supplied by the output capacitors. The controller recognizes immediately the load transient and increases the duty cycle, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): VOUT = IOUT * ESR A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: I OUT L V OUT = ----------------------------------------------------------------------------------4 C OUT ( V IN D MAX - V OUT ) Where DMAX is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. INDUCTOR DESIGN The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: V IN - V OUT V OUT L = ----------------------------- -------------f S W I L V IN Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. The response time is the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for I load transient in case of enough fast compensation network response: L I t a pplic atio n = ----------------------------V IN - V OUT L I t rem ov al = -------------V OUT
2
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available.
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Figure 12. Inductor ripple current vs VOUT
9
L=1.5H, Vin=12V
8
Inductor Ripple [A]
7 6 5 4 3 2 1 0 0.5 1.5 2.5
L=2H, Vin=12V L=3H, Vin=12V L=1.5H, Vin=5V L=2H, Vin=5V L=3H, Vin=5V
3.5
Output Voltage [V]
MAIN CONTROL LOOP The control loop is composed by the Current Sharing control loop and the Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 13 reports the block diagram of the main control loop. Figure 13. Main Control Loop Diagram
+
L1 PWM1 IINFO2 IINFO1 L2 PWM2 ERROR AMPLIFIER 4/5 COMP ZF(S) REFERENCE PROGRAMMED BY VID FB RFB CO RO
1/5
1/5
CURRENT SHARING DUTY CYCLE CORRECTION
+
+ -
D02IN1392
Current Sharing (CS) Control Loop Active current sharing is implemented using the information from Tran conductance differential amplifier in an average current mode control scheme. A current reference equal to the average of the read current (IAVG) is internally built; the error between the read current and this reference is converted to a voltage with a proper gain and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See fig. 14). The current sharing control is a high bandwidth control loop allowing current sharing even during load transients. The current sharing error is affected by the choice of external components; choose precise Rg resistor (1% is
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necessary) to sense the current. The current sharing error is internally dominated by the voltage offset of Tran conductance differential amplifier; considering a voltage offset equal to 2mV across the sense resistor, the current reading error is given by the following equation: I RE AD 2mV ------------------- = --------------------------------------I M AX R SENSE I M AX Where IREAD is the difference between one phase current and the ideal current (IMAX/2). For RSENSE = 4m and IMAX = 40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and Rsense mismatches. Figure 14. Current Sharing Control Loop
+
L1 PWM1
1/5
1/5
CURRENT SHARING DUTY CYCLE CORRECTION
IINFO2 IINFO1
+
COMP
PWM2
L2
D02IN1393
VOUT
Average Current Mode (ACM) Control Loop The average current mode control loop is reported in figure 15. The current information IFB sourced by the FB pin flows into RFB implementing the dependence of the output voltage from the read current. The ACM control loop gain results (obtained opening the loop after the COMP pin): PWM Z F ( s ) ( R DROOP + Z P ( s ) ) G LO O P ( s ) = -------------------------------------------------------------------------------------------------------------------ZF (s ) 1 ( Z P ( s ) + Z L ( s ) ) -------------- + 1 + ----------- R FB A(s) A ( s) Where: R s en se - R DROOP = ------------------ R FB is the equivalent output resistance determined by the droop function; Rg - ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load Ro; - ZF(s) is the compensation network impedance; - ZL(s) is the parallel of the two inductor impedance; - A(s) is the error amplifier gain; 4 V IN - PWM = -- ------------------ * is the ACM PWM transfer function where VOSC is the oscillator ramp amplitude 5 V O SC and has a typical value of 3V Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control loop gain results:

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V IN ZF ( s) ZP ( s ) 4 - Rs G LO O P ( s ) = - -- ------------------ ----------------------------------- ------- + -------------5 V OS C Z P ( s ) + Z L ( s ) Rg R FB With further simplifications, it results:

V IN Z ( s ) R o + R DROOP 1 + s Co ( R DROOP //Ro + ESR ) 4 - FG L OO P ( s ) = - -- ------------------ -------------- ------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------RL RL 5 V O SC R FB 2 L L R o + -----s C o -- + s --------------- + Co ESR + Co ------ + 1 2 2 2 2 Ro Considering now that in the application of interest it can be assumed that Ro>>RL; ESR<R FB V O SC 5 L R F = ---------------------------------- -- T ------------------------------------------------------V IN 4 2 ( R DROOP + ESR )
L C o -2 C F = ------------------RF
Figure 15. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right)
dB
ZF CF
IFB RF
GLOOP
RFB VCOMP REF
K ZF(s)
PWM
L/2 d*VIN * Cout ESR
VOUT
LC Z T
Rout
4 VI N 1 K = -- --------------- ---------5 Vo sc R FB
dB
LAYOUT GUIDELINES Since the device manages control functions and high-current drivers, layout is one of the most important things
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to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. Integrated power drivers reduce components count and interconnections between control functions and drivers, reducing the board space. Here below are listed the main points to focus on when starting a new layout and rules are suggested for a correct implementation.
s
Power Connections.
These are the connections where switching and continuous current flows from the input supply towards the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces. The critical components, i.e. the power transistors, must be located as close as possible, together and to the controller. Considering that the "electrical" components reported in figure are composed by more than one "physical" component, a ground plane or "star" grounding connection is suggested to minimize effects due to multiple connections. Figure 16. Power connections and related connections layout guidelines (same for both phases)
VIN
Rgate HGATEx PHASEx L COUT D CIN LOAD HS
Rgate LGATEx PGNDx
LS
a. PCB power and ground planes areas
BOOTx CBOOTx HS
V IN
PHASEx L +VCC VCC LS D CIN SGND CVCC COUT LOAD
b. PCB small signal components placement
Fig. 16a shows the details of the power connections involved and the current loops. The input capacitance (CIN),
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or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are required.
s
Power Connections Related.
Fig.16b shows some small signal components placement, and how and where to mix signal and power ground planes. The distance from drivers and mosfet gates should be reduced as much as possible. Propagation delay times as well as for the voltage spikes generated by the distributed inductance along the copper traces are so minimized. In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a consequence, the higher are the voltage spikes corresponding to the gate PWM rising and falling signals. Even if these spikes are clamped by inherent internal diodes, propagation delays, noise and potential causes of instabilities are introduced jeopardizing good system behavior. One important consequence is that the switching losses for the high side mosfet are significantly increased. For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance (see fig 17). In addition, since the PHASEx pin is the return path for the high side driver, this pin must be connected directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets, the return path is the PGND pin: it can be connected directly to the power ground plane (if implemented) or in the same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power ground plane is implemented) must also be designed to handle current peaks in excess of 2A (30 mils wide is suggested). Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system efficiency. Figure 17. Device orientation (left) and sense nets routing (right)
Towards HS mosfet
(30 mils wide)
To LS mosfet
(or sense resistor)
Towards LS mosfet
(30 mils wide)
Towards HS mosfet
(30 mils wide)
To LS mosfet
(or sense resistor)
To regulated output
The placement of other components is also important: - The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to minimize the loop that is created. - Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins. - Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capacitor sustains the peak currents requested by the low-side mosfet drivers. - Refer to SGND all the sensible components such as frequency set-up resistor (when present) and also the optional resistor from FB to GND used to give the positive droop effect. - Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation effect and to ensure the right precision to the regulation when the remote sense buffer is not used.
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- An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in reducing noise. - PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be observed on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device can absorb energy and it can cause damages. The voltage spikes must be limited by proper layout, the use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber network on the low side mosfets, to a value lower than 26V, for 20nSec, at FSW of 600kHz max.
s
Current Sense Connections.
Remote Buffer: The input connections for this components must be routed as parallel nets from the FBG/FBR pins to the load in order to compensate losses along the output power traces and also to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load, will cause a non-optimum load regulation, increasing output tolerance. Current Reading: The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx pins in order to limit the noise injection into the device. The PCB traces connecting these resistors to the reading point must be routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important to avoid any offset in the measurement and to get a better precision, to connect the traces as close as possible to the sensing elements, dedicated current sense resistor or low side mosfet RdsON. Moreover, when using the low side mosfet RdsON as current sense element, the ISENx pin is practically connected to the PHASEx pin. DO NOT CONNECT THE PINS TOGETHER AND THEN TO THE HS SOURCE! The device won't work properly because of the noise generated by the return of the high side driver. In this case route two separate nets: connect the PHASEx pin to the HS Source (route together with HGATEx) with a wide net (30 mils) and the ISENx pin to the LS Drain (route together with PGNDSx). Moreover, the PGNDSx pin is always connected, through the Rg resistor, to the PGND: DO NOT CONNECT DIRECTLY TO THE PGND! In this case the device won't work properly. Route anyway to the LS mosfet source (together with ISENx net). Right and wrong connections are reported in Figure 18. Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter. Figure 18. PCB layout connections for sense nets
NOT CORRECT
VIA to GND plane To PHASE connection
CORRECT
To LS Drain and Source To HS Gate and Source
Wrong (left) and correct (right) connections for the current reading sensing nets.
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Demo Board Description The L6919E demo board shows the operation of the device in a dual phase application. This evaluation board allows output voltage adjustability (0.800V - 1.550V) through the switches S0-S4 and high output current capability. The board has been laid out with the possibility to use up to two D2PACK mosfets for the low side switch in order to give maximum flexibility in the mosfet choice. The four layers demo board's copper thickness is of 70m in order to minimize conduction losses considering the high current that the circuit is able to deliver. Demo board schematic circuit is reported in Figure 19. Figure 19. Demo Board Schematic
Vin
JP6
GNDin
DZ1
JP1 JP2
R16
VCCDR VCC
R11 2 6 C7
BOOT1 BOOT2
C9,C10 C11..C13
Vcc C5 GNDcc D4 C8
D3
C6
5
UGATE1
24
UGATE2
C4 L1
Q2 R15
PHASE1
4 3 R18
LGATE1
25 R14
PHASE2
Q4
C3 L2 VoutCORE C14, C23 R19 R20 GNDCORE
26
LGATE2
R17 Q3 R12 D2 Q3a R3
Q1 D1 Q1a R6
PGNDS1
1 R13
ISEN1
27
ISEN2
13
U1
16
PGNDS2
14 R5 S4 S3 S2 S1 S0 To pin VCC
VID4
L6919E 15
28 23 10
R1
PGND
R4
22
VID3
PGOOD
21
VID2
PGOOD
VSEN
20
VID1 VID0 OSC / INH
R10
FB
19 18 17 9
JP3
R7
C24
JP4 JP5
R21
R8 C2
COMP
R2
SGND
C1
R9
7 11
FBR
12
8
FBG
FBG FBR
Several jumpers allow setting different configurations for the device: JP3, JP4 and JP5 allow configuring the remote buffer as desired. Simply shorting JP4 and JP5 the remote buffer is enabled and it senses the output voltage on-board; to implement a real remote sense, leave these jumpers open and connect the FBG and FBR connectors on the demo board to the remote load. To avoid using the remote buffer, simply short all the jumpers JP3, JP4 and JP5. Local sense through the R7 is used for the regulation. The input can be configured in different ways using the jumpers JP1, JP2 and JP6; these jumpers control also the mosfet driver supply voltage. Anyway, power conversion starts from VIN and the device is supplied from V CC (See Figure 20). Figure 20. Power supply configuration
To Vcc pin
Vin
JP6
To HS Drains (Power Input) To BOOTx (HS Driver Supply)
DZ1
JP1 JP2
GNDin
Vcc GNDcc
To VCCDR pin (LS Driver Supply)
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Two main configurations can be distinguished: Single Supply (VCC=VIN=12V) and Double Supply (VCC=12V VIN=5V or different). - Single Supply: In this case JP6 has to be completely shorted. The device is supplied with the same rail that is used for the conversion. With an additional zener diode DZ1 a lower voltage can be derived to supply the mosfets driver if Logic level mosfet are used. In this case JP1 must be left open so that the HS driver is supplied with VIN-VDZ1 through BOOTx and JP2 must be shorted to the left to use VIN or to the right to use VIN-VDZ1 to supply the LS driver through VCCDR pin. Otherwise, JP1 must be shorted and JP2 can be freely shorted in one of the two positions. - Double Supply: In this case VCC supply directly the controller (12V) while VIN supplies the HS drains for the power conversion. This last one can start indifferently from the 5V bus (Typ.) or from other buses allowing maximum flexibility in the power conversion. Supply for the mosfet driver can be programmed through the jumpers JP1, JP2 and JP6 as previously illustrated. JP6 selects now VCC or VIN depending on the requirements. Some examples are reported in the following Figures 21 and 22. Figure 21. Jumpers configuration: Double Supply
Vcc = 12V
Vin = 5V GNDin
JP6
HS Drains = 5V HS Supply = 5V
DZ1
JP1 JP2
Vcc = 12V GNDcc
VCCDR (LS Supply) = 5V
(a) VCC = 12V; VBOOTx = VCCDR = VIN = 5V
Vcc = 12V
Vin = 5V GNDin
JP6
HS Drains = 5V HS Supply = 12V
DZ1
JP1 JP2
Vcc = 12V GNDcc
VCCDR (LS Supply) = 12V
(b) VCC = VBOOTx = VCCDR = 12V; VIN = 5V
Figure 22. Jumpers configuration: Single Supply
Vcc = 12V
Vin = 12V GNDin
JP6
HS Drains = 12V HS Supply = 5.2V
DZ1 6.8V
JP1 JP2
Vcc = Open GNDcc
VCCDR (LS Supply) = 12V
(a) VCC = VIN = VCCDR = 12V; VBOOTx = 5.2V
Vcc = 12V
Vin = 12V GNDin
JP6
HS Drains = 12V HS Supply = 12V
DZ1
JP1 JP2
Vcc = Open GNDcc
VCCDR (LS Supply) = 12V
(b) VCC = VIN = VBOOTx = VCCDR = 12V
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PCB AND COMPONENT LAYOUT Figure 23. PCB and Components Layouts (Dimensions: 10.8mm x 8.2mm)
Component Side
Internal PGND Plane
Internal SGND Plane
Solder Side
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CPU Power Supply: 5 to 12VIN; 1.2VOUT; 45ADC Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast reaction, this helps in reducing output and input capacitor. Inductance value is also reduced. A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compensation network. Considering the high output current, power conversion will start from the 12V bus. - Current Reading Network and Over Current: Since the maximum output current is IMAX = 45A, the over current threshold has been set to 45A (22.5A x 2)in the worst case (max mosfet temperature). Since the device limits the valley of the triangular ripple across the inductors, the current ripple must be considered too. Considering the inductor core saturation, a current ripple of 10A has to be considered so that the OCP threshold in worst case becomes OCPx=17A (22.5A-5A). Considering to sense the output current across the low-side mosfet RdsON, SUB85N03L-04P has 4.3m max at 25C that becomes 5.6m at 100C considering the temperature variation; the resulting transconductance resistor Rg has to be:
R d sO N 5.6m Rg = I OCPx ----------------- = 17 ------------- = 2.7k 35 35
(R3 to R6)
- Droop function Design: Considering a voltage drop of 70mV at full load, the feedback resistor RFB has to be: 70mV R FB = --------------- = 1k (R7) 70A - Inductor design: Transient response performance needs a compromise in the inductor choice value: the biggest the inductor, the highest the efficient but the worse the transient response and vice versa. Considering then an inductor value of 0.8H, the current ripple becomes: Vin - Vout d 12 - 1.2 1.2 1 I = ---------------------------- ----------- = -------------------- ------- ------------ = 6.5A (L1, L2) Fsw 12 200k L 0.8 - Output Capacitor: Five Rubycon MBZ (2200F / 6.3V / 12m max ESR) has been used implementing a resulting ESR of 2.4m resulting in an ESR voltage drop of 45A * 2.4m = 108mV after a 45A load transient. - Compensation Network: A voltage loop bandwidth of 20kHz is considered to let the device fast react after load transient. The RF CF network results:
R F B V O S 5 L 1K 2 5 0.8 --RF = ----------------------------- -- T ------------------------------------------------------ = -------------- -- 20K 2 --------------------------------------------------------------- = 2.0k (R8) VIN 12 4 2 ( RDROOP + ESR ) 4 5.6m 2 ------------- 1.2k + 2.4m 2.7
CF
1 L Co -6 2200 -----22 = ---------------------------------------- = 33nF (C2) = ------------------RF 2k
Further adjustments can be done on the work bench to fit the requirements and to compensate layout parasitic components.

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Part List R2 R1, R20,R21 R3, R4, R5, R6 R7 R8 R9 R10 R11 R12 to R19 C1 C2 C3, C4 C5, C6, C7, C8 C9, C10 C11 to C13 C14 to C18 C24 L1, L2 U1 Q1, Q3 Q2, Q4 D1, D2 D3, D4 S0,S4 S1,S2,S3
147k Not Mounted 2.7k 1k 1.8k 47k 510 82 0 Not Mounted 22n 100n 1 10 or 22 / 16V 1800 / 16V 2200 / 6.3V 100n 0.8 L6919E SUB85N03-04P SUB70N03-09BP STPS340U 1N4148 Short Open
1% 1% 1% 1%
SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805
SMD 0805 SMD 0805 SMD 0805 Ceramic SMD 1206 TDK Multilayer Ceramic SMD 1206 Rubycon MBZ Radial 10x23 Rubycon MBZ Radial 10x20 SMD 0805 77121 - 4Turns STMicroelectronics Vishay Vishay STMicroelectronics STMicroelectronics
SO28 D2PACK D2PACK SMB SOT23
STATIC PERFORMANCES Figure 24 shows the demo board measured efficiency versus load current in steady state conditions without airflow at ambient temperature. Figure 24. System Efficiency
90 85 80
Efficiency [%]
75 70
c
65 60 55 50 0 5 10 15 20 25 30 35 40 45
Output Current [A]
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Figure 25 shows the mosfets temperature versus output current in steady state condition without any air-flow or heat sink. It can be observed that the mosfets are under 100C in any conditions. Load regulation is also reported from 10A to 45A. Figure 25. Mosfet Temperature and Load Regulation
100 C] 90 80 70 60 50 40 30 High-side MOS Q2 High-side MOS Q4 Low -side MOS Q3 Low -side MOS Q1
1.250 1.240 1.230 Vout [V] 1.220 1.210 1.200 1.190 1.180 1.170
MOS Temperature [
o
20 0 5 10 15 20 25 30 35 Output Current [A] 40 45
0
5
10
15
20
25
30
35
40
45
Output Current [A]
DYNAMIC PERFORMANCES Figure 26 shows the system response to a load transient from 3A to 45A. The output voltage is contained in the 50mV range. Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR. Figure 26. 3A to 45A Load Transient Response
Figure 27 shows the system response to a VID transient from 1.200V to 0.800V and vice versa at minimum load (3A). Figure 27. Dynamic VID Response
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DEMO BOARD ENHANCEMENTS: 1.200V / 52A CPU Power Supply Considering the same application schematic, minor changes can be done to achieve the 52A thermal output current required by AMD Hammer processor core. Part list has been modified as follow: Part List R2 R1, R20,R21 R3, R4, R5, R6 R7 R8 R9 R10 R11 R12 to R19 C1 C2 C3, C4 C5, C6, C7, C8 C9, C10 C11 to C13 C14 to C18 C24 L1, L2 U1 Q1, Q1a, Q3, Q3a Q2, Q4 D1, D2 D3, D4 S0,S4 S1,S2,S3
147k Not Mounted 1.5k 1k 1.8k 47k 510 82 0 Not Mounted 10n 100n 1 10 or 22 / 16V 1800 / 16V 2200 / 6.3V 100n 0.8 L6919E SUB85N03-04P SUB70N03-09BP STPS340U 1N4148 Short Open
1% 1% 1% 1%
SMD 0806 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805
SMD 0805 SMD 0805 SMD 0805 Ceramic SMD 1206 TDK Multilayer Ceramic SMD 1206 Rubycon MBZ Radial 10x23 Rubycon MBZ Radial 10x20 SMD 0805 77121 - 4Turns STMicroelectronics Vishay-Siliconix Vishay-Siliconix STMicroelectronics STMicroelectronics
SO28 D2PACK D2PACK SMB SOT23
STATIC PERFORMANCES Figure 28 shows the demo board measured efficiency versus load current in steady state conditions without airflow at ambient temperature. Figure 28. System Efficiency
90 85 80 75 Efficiency [%] 70 65 60 55 50 45 40 0 5 10 15 20 25 30 35 40 45 50 55 60 Output Current [A]
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Figure 29 shows the mosfets temperature versus output current in steady state condition without any air-flow or heat sink. It can be observed that the mosfets are under 105C in any conditions. Load regulation is also reported from 10A to 55A. Figure 29. Mosfet Temperature and Load Regulation.
115 105
oC]
High-side M OS Q2 High-side M OS Q4 Lo w-side M OS Q1
1.235 1.225 1.215 Vout [V] 1.205 1.195 1.185 1.175 1.165 1.155
95 85 75 65 55 45 35 25 0 5
MOS Temperature [
Lo w-side M OS Q3
10 15 20 25 30 35 40 45 50 55 60 Output Current [A]
0
5 10 15 20 25 30 35 40 45 50 55 60 Output Current [A]
Figure 30 shows the system response to a load transient from 3A to 45A. The output voltage is contained in the 50mV range. Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR. Figure 30. 3A to 45A Load Transient Response
Figure 31 shows the system response to a VID transient from 1.200V to 0.800V and vice versa at minimum load (3A). Figure 31. Dynamic VID Response
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DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO28
8 (max.)
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved
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